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November 3, 2026
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One third: The yield gap facing Chinese memory makers without EUV

Chinese chipmakers are achieving advanced nodes through multiple DUV exposures, but the method significantly reduces output efficiency and increases production costs.

By Javier Cabrera ·

Illustration for: One third: The yield gap facing Chinese memory makers without EUV
Illustration generated for this article, not a news photograph.

Chinese memory manufacturer CXMT currently produces only about one-third as many bits per wafer as its Western competitors, a disparity that highlights the efficiency costs of bypassing extreme ultraviolet lithography. This figure, cited in a June report by Morgan Stanley, serves as a clear indicator of the limitations inherent in China's current manufacturing capabilities. The bank described access to advanced lithography equipment as a hard ceiling for the development of memory technologies within the country.

The primary constraint stems from export controls that have excluded ASML's most advanced EUV machines from the Chinese market. ASML is the sole producer of these tools, which utilize 13.5nm wavelength light to print the finest features on modern processors. Consequently, Chinese chipmakers have relied on older deep ultraviolet equipment. Experts estimate that the technological gap between China and Western nations in this specific area stands at five years or more, making the absence of EUV a significant bottleneck for cutting-edge chip production.

Despite these hurdles, Chinese firms have demonstrated unexpected progress by employing multiple patterning techniques. This method involves splitting intricate chip layers into several simpler patterns and building them up step by step. A 2023 teardown of the Huawei Mate 60 Pro revealed that its Kirin 9000S processor was manufactured by SMIC using a second-generation 7nm class process without EUV. More recent analysis suggests that SMIC has moved its DUV based process closer to the density associated with 5nm manufacturing, although it still lags behind the leading processes from TSMC and Samsung.

The financial and quality implications of this workaround are substantial. Chris Mack, co-founder and CTO of semiconductor firm Fractilia, noted that while three exposures on a 193 immersion tool may cost similar to one EUV pass, four masks make EUV the cheaper option. Each additional exposure introduces opportunities for defects and accumulated overlay errors. Designers often add space around features to compensate for these variations, which enlarges the chip and reduces the number of dies per wafer. Mack emphasized that manufacturers sell dies, not wafers, making this reduction a costly outcome when wafers cost tens of thousands of dollars each.

DUV technology still holds potential for further advancement in certain areas. Micron previously developed its 1-alpha DRAM without EUV, using tight process control and multiple patterning, a feat Mack described as pushing 193nm technology farther than any other memory maker. Morgan Stanley considers CXMT's planned move to 1-alpha DRAM, intended for HBM3e, achievable without EUV. Furthermore, researcher Douglas Fuller from Copenhagen Business School expects that advanced packaging will allow firms to use DUV for the latest DRAM generations by the end of the decade.

However, the limits of DUV are becoming apparent as nodes shrink. Micron eventually adopted EUV for its 1-gamma DRAM, which delivers more than 30% greater bit density per wafer than the previous generation. Mack expressed skepticism about the economic viability of 3nm or 2nm nodes without EUV, citing stochastic effects that require higher exposure doses and greater costs. He stressed that while memory is easier to optimize than logic, China could progress significantly if it designed products around the full 193 immersion ecosystem.

Outlook for the industry suggests continued growth through capacity expansion rather than immediate technological parity. Morgan Stanley projects that CXMT will maintain its 1-alpha process without EUV but will increase its share of global DRAM bit supply from 14% in 2026 to 16% in 2028 through new greenfield capacity. The bank also anticipates that China's self-sufficiency in AI chips will rise from 42% in 2025 to 70% by 2030. While gaps in EUV, high bandwidth memory, and advanced software will persist, Chinese chipmakers are expected to keep pushing DUV limits, accepting larger dies and poorer yields as part of the strategy.

Source: Tom's Hardware

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