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November 4, 2026
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Micron aims to double data density in 2027 memory chips

The new G11 NAND uses wafer bonding to reach 42 Gb/mm2 and 5,400 MT/s speeds.

By Amelia Clarke ·

Illustration for: Micron aims to double data density in 2027 memory chips
Illustration generated for this article, not a news photograph.

Micron plans to double the storage capacity of its flash memory by the end of 2027. The company outlined its next generation, labeled G11, at an industry event this week. The new chips are designed to hold roughly twice as much data as the current G9 generation.

The technical shift involves a move from approximately 21 Gb/mm2 to 42 Gb/mm2 in triple-level-cell form. Input/output speeds are projected to rise by up to 50 percent, jumping from 3,600 MT/s to 5,400 MT/s. Micron also stated that the energy required to transfer each bit should drop by more than 25 percent.

These specifications aim to outpace competitors. Kioxia and Samsung are developing their next-generation products, known as BiCS10 and V10 respectively, but Micron claims G11 offers a larger density advantage. The improvements target high-capacity solid-state drives for data centers and consumer devices. They also address the growing demand for storage in artificial intelligence workloads, which require high bandwidth and low power usage.

The core of the design is a new manufacturing method called wafer-on-wafer bonding. This technique allows engineers to build the memory array and the peripheral logic on separate wafers. Each wafer uses a process optimized for its specific function before the two are bonded together. While Micron has used CMOS-under-array designs in the past, bonding provides more flexibility to optimize both components independently.

Scott DeBoer, president and chief technology and products officer at Micron, confirmed the strategy. He noted that the company had previously committed to adopting the technology when it became cost-effective. "This is the right timing for that technology," DeBoer said. He described G11 as the world's most advanced NAND.

The chips will feature more than 400 layers, though Micron has not disclosed the exact count of active wordlines or memory decks. The company expects to share detailed technical specifications in 2027 as high-volume production begins. DeBoer indicated that future generations will continue scaling in all three dimensions using new high-mobility materials and denser cell architectures.

Source: Tom's Hardware

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